The present disclosure generally relates to semiconductor devices, and particularly to a field effect transistor containing a composite gate electrode including a nitride of an aluminum-containing metallic alloy, and methods of manufacturing the same.
The scaling of a gate stack including a high dielectric constant (high-k) dielectric material and a metallic electrode has been limited by a correlation between an inversion thickness (Tinv) and a linear threshold voltage (Vtlin). The inversion thickness (Tinv) refers to the thickness of an equivalent thermal silicon oxide layer that provides the same incremental inversion charge density per gate voltage swing as the high-k dielectric material. The linear threshold voltage (Vtlin) is defined as a gate to source voltage that is needed to provide an areal source-to-drain current density of 300 nA×(W/L) at a drain-to-source voltage of 50 mV in an n-type field effect transistor that does not suffer from short channel effects, or a gate to source voltage that is needed to provide an areal source-to-drain current density of 90 nA×(W/L) at a drain-to-source voltage of 50 mV in a p-type field effect transistor that does not suffer from short channel effects. W refers to the width of the channel of the field effect transistor, and L refers to the length of the channel of the field effect transistor. For p-type field effect transistors, the more negative the linear threshold voltage, the lesser the inversion thickness of a combination of a high-k gate dielectric and a metallic gate electrode. A limit established by a correlation curve between the inversion thickness and the linear threshold voltage as established employing a HfO2 high-k dielectric material and a TiN gate electrode has not been broken by any other combinations of high-k gate dielectric materials and metal gate materials so far.